Logic Synthesis for Reducing Leakage Power Consumption under Workload Uncertainty

Runtime leakage control is gaining in importance, and recent work has demonstrated the possibility of reducing leakage via synthesis and post-synthesis optimizations. These techniques utilize the leakage dependence on state vectors and synthesis the circuit that minimizes power of the most-likely circuit configuration using state probabilities. In this paper we provide empirical evidence using a microprocessor simulator running a variety of applications that the state probabilities are best described as belonging to an interval. Under such interval description of state probability, one can utilize a proxy leakage metric which we define to be the sum of the worst-case mean leakages of all the gates under the feasible probability scenario. We propose a logic synthesis (technology mapping) algorithm under the delay constraint such that proxy metric is minimized across all the feasible realization of the primary input state probabilities. This metric helps to reduce the sensitivity of the leakage optimized mapping to a specific point probability for the primary input signals. We formulate and develop a new technology mapping algorithm to minimize robust mean leakage in the framework of recently introduced robust dynamic programming. An efficient solution is given. The complexity of this approach is linear in the circuit size. The results show that improvements up to 16% can be obtained in leakage.